\doxysubsubsubsection{RCCEx I2\+C4 Clock Source }
\hypertarget{group___r_c_c_ex___i2_c4___clock___source}{}\label{group___r_c_c_ex___i2_c4___clock___source}\index{RCCEx I2C4 Clock Source@{RCCEx I2C4 Clock Source}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
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\Hypertarget{group___r_c_c_ex___i2_c4___clock___source_gaad7e10f8c163af6e2bf7754e60317fbc}\label{group___r_c_c_ex___i2_c4___clock___source_gaad7e10f8c163af6e2bf7754e60317fbc} 
\#define {\bfseries RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+SRDPCLK4}~(0x00000000U)
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\Hypertarget{group___r_c_c_ex___i2_c4___clock___source_gaac1a7c74fc89ee94914fdb94436472e1}\label{group___r_c_c_ex___i2_c4___clock___source_gaac1a7c74fc89ee94914fdb94436472e1} 
\#define {\bfseries RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+D3\+PCLK1}~RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+SRDPCLK4
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\Hypertarget{group___r_c_c_ex___i2_c4___clock___source_ga49995d80cf908c925fb62df0b3516f4d}\label{group___r_c_c_ex___i2_c4___clock___source_ga49995d80cf908c925fb62df0b3516f4d} 
\#define {\bfseries RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+PLL3}~RCC\+\_\+\+SRDCCIPR\+\_\+\+I2\+C4\+SEL\+\_\+0
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\Hypertarget{group___r_c_c_ex___i2_c4___clock___source_gab3544835d7916cd3316a12bd1d9a6f11}\label{group___r_c_c_ex___i2_c4___clock___source_gab3544835d7916cd3316a12bd1d9a6f11} 
\#define {\bfseries RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+HSI}~RCC\+\_\+\+SRDCCIPR\+\_\+\+I2\+C4\+SEL\+\_\+1
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\Hypertarget{group___r_c_c_ex___i2_c4___clock___source_ga7f0a63e050f895a300134900e1b03293}\label{group___r_c_c_ex___i2_c4___clock___source_ga7f0a63e050f895a300134900e1b03293} 
\#define {\bfseries RCC\+\_\+\+I2\+C4\+CLKSOURCE\+\_\+\+CSI}~(RCC\+\_\+\+SRDCCIPR\+\_\+\+I2\+C4\+SEL\+\_\+0 \texorpdfstring{$\vert$}{|} RCC\+\_\+\+SRDCCIPR\+\_\+\+I2\+C4\+SEL\+\_\+1)
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\doxysubsubsubsubsection{Detailed Description}
